The present invention relates to the assembly of micro- and nano-scale devices and components suspended in a dielectric medium onto a substrate patterned with electrodes that are used to attract and align the devices and components. The substrate on which the devices and components are assembled could contain existing active circuitry to which the components or devices are integrated or the substrate could be used as a template for assembly of more complex standalone two and three-dimensional structures.
As the market for low-cost and/or high-performance/density micron- and nano-scale electronic and electromechanical integrated circuits increases, many new assembly and integration techniques must be developed. As an example, at the micron-scale, it has become increasingly important to manufacturers of compound semiconductors to integrate high-performance optoelectronic and/or radio frequency components onto dissimilar substrates. Often these substrates contain active circuitry to which the compound semiconductor devices must be integrated monolithically to improve system performance and reduce assembly costs. While current integration strategies often rely on pick-and-place mechanical assembly, new low-cost parallel assembly techniques are being investigated and commercialized.
In addition to integration of relatively large-scale devices and components, there has also been a continued interest in scaling to nanometer dimensions the size of individual devices. Current semiconductor manufacturing technology typically relies on integration of silicon devices using photolithographic techniques. Recently, there has been increasing interest in novel nano- and molecular electronic circuit topologies. One of the limiting factors is the integration of the devices with nanometer scale interconnects. Alternative approaches based on assembly of metallic nanowires and carbon nanotubes have been proposed, but few assembly strategies exist.
In reference to integration of micron-scale devices and components, heterogeneous integration of high performance electrical, optoelectronic, and micro-electro-mechanical devices together onto the same substrate is critical for the development of high-performance microsystems. Of particular interest is integrating these types of devices with silicon CMOS technology, in order to increase the number of on-wafer functions available, and ultimately reduce the size, weight, and cost of micro-device based systems. As the dimensions of micro-electronic and micro-electromechanical devices and systems decrease, and as their complexity increases, there is a need to use self assembly techniques to simplify the assembly and processing of these devices.
Several promising approaches have been presented for integration of different types of micro-devices on the same substrate, including selective area growth, flip-chip bonding, epitaxial lift-off (ELO), fluidic self-assembly and electrostatic alignment. However, each of these approaches has drawbacks and technological issues that limit their utility in actual applications.
Selective area growth was investigated early as a potential method of heterogeneous integration. After the front-end, high-temperature, portion of the silicon CMOS process is completed, epitaxial material is grown on a buffer island. This procedure results in devices that can be processed in conjunction with the back-end silicon process. However, due to lattice mismatch and thermal property mismatch, the devices grown on silicon are not as good as devices grown on a lattice-matched substrate.
Flip chip bonding is commonly used for aligning individual devices. In this process, individual die are diced from growth wafers and mounted upside-down on a host substrate. The fully processed active devices are individually placed onto bonding sites with a mechanical pick-and-place tool. The devices are held into place by solder bonding, and then the substrate is removed by etching, if desired. Because this process involves serial manipulation and alignment of individual device die, it is time consuming and expensive.
Other procedures for heterogeneous integration include epitaxial transfer procedures such as ELO and applique. For both processes, an epitaxial layer is generally released from its growth substrate, either by etching a sacrificial layer (ELO) or by etching the substrate down to an etch-stop layer (applique). The layer, which is typically supported by a wax or polymer membrane, is then bonded to the host substrate through van der Waals bonding or with a metal bond. Depending upon the process requirements, the devices can be processed either before or after the transfer of the epitaxial layer to the host substrate. ELO and applique techniques, which have been used for the integration of optical devices with silicon CMOS, are disadvantageous for at least two reasons. First, handling extremely thin epitaxial layers is difficult and tedious. Second, any pre-processed devices need to be aligned to existing circuitry on the host substrate, which is difficult and time-consuming when compounded with the thinness of the epitaxial film.
Another procedure that can be used to transfer an entire epitaxial layer is wafer bonding. Typically, an epitaxial structure is grown upside down on a growth wafer. The growth wafer and the host wafer are bonded together, and the growth wafer is removed to expose the epitaxial layers. The epitaxial layers are then processed to create the devices. Unfortunately, bonded wafers suffer from thermal limitations, due to thermal expansion mismatch of the wafers, and due to different thermal budgets for the two different materials.
For successful, efficient heterogeneous integration, a process that will align separate discrete die without individual manipulation of the devices is required. There have been two approaches published that meet these requirements. These approaches are fluidic self-assembly and vector potential parts manipulation.
Fluidic self-assembly, in which carefully etched device die are mated to a substrate with etched holes of matching dimensions, is one process that will align separate devices without individual manipulation. The host substrate is patterned with deep holes that match the shape of the device die. The specially shaped device die are lifted-off of the growth substrate, suspended in a solution, and flowed over the host substrate. The parts align themselves into the holes in the host substrate. However, fluidic self-assembly requires that the device die are trapezoidally shaped, to match the openings in the substrate. This shape requirement is a task that is difficult to achieve and adds several processing steps, such as ion-milling.
Another process that allows for the alignment of separate device die is potential-driven assembly. This process uses a potential, most often electrostatic, to direct and place parts. Parts are placed on a vibrating stage and are attracted to potential wells on the substrate. As the vibration is reduced, the parts xe2x80x9cannealxe2x80x9d into place. At this time, this technique has only been used to manipulate relatively large parts using high voltages in a specially prepared alignment fixture.
While the techniques discussed above describe approaches that either are in use or under development for the alignment of micron-scale objects such as semiconductor devices and die, a new area of research is developing in nanometer- and molecular-scale electronics for ultra-high density and performance logic and memory circuits. In these applications present photolithographic techniques grow exponentially more expensive with decreasing feature size, and may never reach the dimensions required for this new technology. Based on these limitations, it has been suggested that future device integration may be based on alternative approaches that rely on assembly of nanometer-scale colloidal particles such as isotropic and anisotropic metallic particles and carbon nanotubes. Therefore, research has focused on developing new chemical and electric field-assisted assembly techniques to control the placement of these particles with the precision required to form well-ordered logic and memory circuits.
Following the pioneering work of Pohl, described in H. A. Pohl, J. Appl. Phys. 22, 869 (1951), and H. A. Pohl, Dielectrophoresis (Cambridge University Press, 1978), nonuniform electric fields have been used to manipulate dielectric particles that are suspended in liquid media.
While considerable effort has been devoted to separating biological particles, dielectrophoresis has also been used recently to (1) orient colloidal dispersions of nanometer-scale rod-shaped gold particles in an electrooptical cell and (2) to align carbon nanotubes between biased electrodes on a glass substrate. In the second application, the nanotubes aligned randomly along the electrode edge with their length oriented in the direction of the electric field.
Despite the interesting prior art developments in this field of micro-devices, the ultimate in optimization has yet to be realized. Accordingly it is a primary object of this invention to provide a method of combining different devices and materials on a single substrate, with materials and processing optimized for each individual device. It is a further object of this invention to provide an efficient, rapid method of placing, aligning, and interconnecting separate discrete components.
The foregoing and other problems are overcome and the objects of the invention are realized by a process of manufacturing, including a technique of assembling parts of an apparatus. The technique includes forming electrode structures on a substrate, suspending the apparatus parts in a dielectric medium near the electrode structure, and applying a non-uniform electric field to align the parts in pre-determined positions in accordance with the desired apparatus topography. The mechanism of alignment is near-field electric field forces developed between the electrode structures and the parts being aligned, either singly, or in combination with longer range forces such as, for example, dielectrophoretic forces or fludic self-assembly forces. While the parts may include semiconductor die or nanometer wires for making connections to devices, the invention is not limited to those devices but may include any device capable of being assembled in this manner.